The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to vertically stacked transistors and the formation thereof.
As semiconductor integrated circuits (ICs) or chips become smaller, the implementation of stacked transistors in semiconductor devices has increased. Nanosheet transistors are non-planar semiconductor devices that utilize two-dimensional nanostructures (e.g., nanosheets or nanowires) with a thickness range on the order of about 1 nanometer (nm) to about 100 nm. Nanosheet transistors have a reduced footprint compared to conventional planar-type semiconductor devices. Accordingly, nanosheet transistors are seen as an option for reducing the footprint of semiconductor devices to 7 nanometers and beyond.